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Firmware emulation / browser labs / 17 Oct 2026

A clean boot is not a silicon passport.

esp32sim can boot an unmodified ESP32 image inside a browser tab. That is useful evidence. Keep device coverage, clock behavior, network reach, physical effects, and failure recovery on separate test cards.

Use the emulator to shorten the loop. Use hardware to close the contracts the emulator does not claim.

The tab ran real firmware

The esp32sim project is a Rust emulator for ESP32, ESP32-S3, ESP32-C3, and ESP32-C6 chips. Its browser build runs the emulator in a Web Worker. The page reads firmware from hosted files or the visitor's disk.

We opened the hosted hello_world demo. The live console showed the ESP32-S3 mask ROM, the ESP-IDF 5.5.4 second-stage bootloader, the application image, and Hello world!. The page reported WebAssembly execution and an emulated-time counter. That proves the hosted demo completed this path in our browser. We did not build the local command-line tool or attach a board.

A boot log proves a boot path. It does not prove every peripheral, clock edge, or fault.

The repository names its cut lines

At revision 142805d5399e0c3cf25995fe21ba524e75a2b3cb, the peripheral table labels blocks as full, partial, stubbed, or absent. UART, timers, flash, crypto blocks, GPIO, display buses, Wi-Fi paths, and board models have different coverage. Bluetooth and the Wi-Fi radio frequency path are not modeled.

The WebAssembly documentation states that the browser build has no direct network address translation because the tab has no host sockets. Firmware can use the virtual access point and subnet. Traffic beyond the emulated gateway is refused unless a separate relay is used. The same document says the execution timing does not establish cycle accuracy.

Good tests have several witnesses

The project does more than compare one boot log. Its test guide lists decoder fixtures, core semantics, peripheral tests, machine tests, golden firmware runs, WebAssembly smoke tests, and selected comparisons against physical boards. The continuous integration workflow builds the workspace, runs Clippy, executes hermetic and golden tests, builds the WebAssembly module, and runs named firmware manifests under Node.

Those layers support different claims. A decoder fixture checks instruction translation. A golden console checks a known run. A hardware trace checks one board, image, state, and observation path. None of them turns every untested device or physical effect into a match.

Keep six contracts

  1. Pin the firmware, ROM, bootloader, partition table, emulator revision, and browser build.
  2. List the CPU, memory map, interrupt path, and every device the test touches.
  3. State whether time means wall time, emulated time, instructions, cycles, or event steps.
  4. Record the virtual network, external relay, refused routes, and packet observations.
  5. Put radio frequency behavior, analog timing, thermal effects, wear, and board-specific faults on the hardware lane.
  6. Inject one failure. Record the expected output, cleanup, and residue check.

Use the browser as the first lane

A browser emulator can give a coding agent a quick, repeatable firmware loop without a board on every desk. Keep the same image and scripted input for the hardware run. Compare the output that matters to the change, not every line that happens to be printable.

If the change touches a stubbed or absent block, stop treating the browser run as release evidence for that behavior. Move the test to a board. Save both receipts so the next person knows where the emulator ended and the hardware check began.

Interactive makeover / fidelity test card

Browser firmware switchyard

Replace one "high fidelity" badge with six independent contracts. The rail drafts a test card. It does not run firmware, compare a board, or approve a release.

Choose the evidence lanes

Payload starts selected because the article pinned the demo and revision. Select only the other contracts your planned test will record.

Fidelity contracts
Test card open1 of 6 selected

Five contracts are still open.

The payload is pinned. Runtime and hardware evidence still need named checks.

Payload
Machine
Clock
Network
Physical
Failure
Completion means structure1 of 6 contractsThe article pins a payload and revision. The card has not collected a runtime trace or board result.

What this component does. It drafts a test card with separate evidence contracts. Selecting every contract means the card structure is ready. It does not attach results, prove physical equivalence, or approve firmware for release.

Sources read / 17 Oct 2026

Evidence bay

Project and source

esp32sim

The repository documents supported chips, browser execution, board models, test layers, peripheral coverage, network limits, and hardware comparisons. Source inspected at revision 142805d5399e0c3cf25995fe21ba524e75a2b3cb.

Inspect the revision / Open the hosted demo
Official platform guide

Espressif QEMU guide

Espressif documents its maintained QEMU fork, the CPU, memory, and several peripheral models, plus IDF commands for running and debugging applications without flashing a board.

Read the guide
Reference emulator

Espressif QEMU fork

The repository identifies the maintained fork and its machine-emulation base. It supplies a second first-party route for understanding ESP32 emulation.

Inspect the repository
Discovery route

Hacker News item 50131189

The official item ID resolves the esp32sim launch and discussion. The thread was used for discovery, not for technical proof.

Open the discussion

Evidence boundary. The esp32sim repository supports claims about its code, documented coverage, and test design. The hosted demo supplied one observed browser run. Espressif documents its separate QEMU route. None of these sources proves that the browser matches every ESP32 board or physical effect.