The chip is a chain of witnesses
The headline on Hacker News says AI can now develop its own inference hardware. The repository supports a narrower and more useful statement. Its authors built an open accelerator project with agent-run architecture tournaments. The project includes SystemVerilog RTL, an instruction set, a bit-exact simulator, a small kernel language, a compiler, host software, and an FPGA card path.
The card is not a fabricated application-specific integrated circuit. It is an FPGA design running on a Xilinx Kintex-7 board. That does not make the result small. It makes the result inspectable. The repository ties source code to a simulator, a bitstream process, qualification scripts, card counters, and token comparisons.
A hardware claim gets stronger when each layer has its own witness and the layers agree.
Start with the contract
The instruction set and simulator define what the machine should do. The README says the simulator is the specification. Tests compare the simulator and RTL at the bit level. That gives reviewers a contract below the model demo and above the wires.
The repository then adds the physical path. Its board guide describes Vivado builds, timing reports, FPGA programming, PCIe setup, staged self-tests, memory checks, soak runs, and token-exact comparisons. The published production image is reported at 133.33 MHz with positive setup and hold slack. Those numbers come from the project. We did not reproduce the licensed Vivado build or run the named card.
Separate a real card run from a local smoke check
The project reports ten models running with real weights on the card. It lists device and wall throughput, DRAM traffic, commit-tagged images, and its measurement method. For LFM2.5-230M with 4-bit weights and an int8 head, the table reports 85.8 device tokens per second and 82.1 wall tokens per second. That is a project measurement on one board and host, not a general accelerator ranking.
Our artifact check covered a different layer. We cloned commit 5b1e646. The tree contains 44 SystemVerilog files, 192 Python files, and 65 files named as Python tests. We installed the Python package dependencies in an isolated environment and ran tests/test_tourney.py. All 70 tests passed in 4.46 seconds. That proves the tournament's Python test file ran on this host. It does not prove RTL correctness, timing closure, card operation, model accuracy, or the published throughput.
The verifier is the real product lesson
The related auto-architecture tournament explains the method behind the work. Agents may edit target RTL and tests. They may not edit the formal harness, FPGA evaluator, benchmark checks, or orchestration code. Each proposal must pass lint, synthesis, simulation, formal checks, and three place-and-route seeds before it can beat the current design.
That boundary matters more than the phrase "developed by AI." An agent can propose and patch. The fixed evaluator decides what survives. Hardware makes this separation easy to see because a fluent answer cannot fake timing closure, bit-exact output, a PCIe link, or a card counter.
Use the rack before repeating the headline
Mark only the evidence you have inspected. A source tree can support a source claim. A simulator run can support simulator behavior. A timing report can support one named build. A card receipt can support one named board, image, host, model, and method. None of those witnesses automatically speaks for the others.